A flash memory device typically performs programming, reading and erasing operations. In order to perform these operations, different bias conditions are typically applied to the flash memory cells of the device.
In particular, typical program bias conditions of a split gate flash memory cell are as follows. Because the split gate flash memory cell may use a source side hot carrier injection method, a voltage of about a threshold voltage Vt, for example, about 1 V, may be applied to a word line that is coupled to the gate of the split gate flash memory cell to be programmed. A predetermined voltage (for example, about 0.4 V) may be applied to a bit line that is coupled to the drain of the split gate flash memory cell to be programmed. A raised program voltage Vpp may be applied to a source line that is coupled to the source of the split gate flash memory cell to be programmed. Accordingly, program current flows from the source line to the bit line when programming is performed.
However, when the number of simultaneously programmed split gate flash memory cells is large, a total program current may be of such magnitude that the level of the program voltage applied to the source line may decrease. As a result, program efficiency may be lowered.
If the voltage level of the program voltage is increased to compensate for the total program current, a disturb phenomenon may occur in which adjacent split gate flash memory cells opposite to each other on the source line are programmed, even when they should not programmed. If the number of split gate memory cells to be simultaneously programmed is small (for example, one or two), the program voltage may not fall, and the adjacent split gate flash memory cells may be directly affected by the program voltage.